1. Field of the Invention
This invention relates to a two-dimensional IDCT circuit which affects two-dimensional inverse discrete cosine transforms (IDCT's) used for processing of signals such as image signals.
2. Description of the Related Art
As augmentation in performance of microprocessors and signal processors proceeds, those processors can be used to realize image signal processing. Above all, with a microprocessor which has a multiplier or a product sum operator built therein, since a product sum operation can be effected using the same clock number as that for addition and subtraction operations, in order to raise the speed of processing, it is desirable not only to decrease the number of multiplication operations but also to minimize the sum of the numbers of addition and subtraction operations and product sum operations.
In order to realize two-dimensional (inverse) DCT by means of a microprocessor or a signal processor, it is a common practice, because of a restriction in the number of internal registers, to first calculate one-dimensional (inverse) DCT in the direction of a row and store results once into an external memory and then read out the results of the processing in the direction of a row from the memory and perform a one-dimensional (inverse) DCT. In this instance, in order to prevent an increase of the calculation amount or the hardware amount, it is a common practice to process the results of the calculation in the direction of a row with a single precision when it is stored into the external memory. Consequently, errors are produced in calculation. One of the methods of suppressing the total number of product sum operations and addition and multiplication operations while suppressing such operation errors is disclosed in "A Study on Fast 2D (I)DCT Algorithm", Collection of Drafts for the Engineering Sciences Society of the Institute of Electronics, Information and Communication Engineers of Japan in 1995, p.88.
FIG. 10 is in block diagram showing an exemplary one of a conventional two-dimensional IDCT circuit. Referring to FIG. 10, an M.times.N two-dimensional IDCT operator 2 receives M.times.N (M and N are natural numbers) DCT coefficients as inputs thereto and effects M.times.N-point two-dimensional inverse discrete cosine transforms. The M.times.N two-dimensional IDCT operator 2 calculates to the kth bit of the fraction part, and results of the calculation of the M.times.N two-dimensional IDCT operator 2 are rounded to integers by an adder 19 and a shift operator 3. To this end, the adder 19 adds 1 to the k-1th bit as counted from the least significant bit for all of output data of the M.times.N two-dimensional IDCT operator 2. The shift operator 3 shifts the outputs of the adder 19 rightwardly by k bits.
In the conventional circuit described above, in order to round results of calculation calculated to the kth bit of the fraction part, the adder 19 adds 0.5 to all of the M.times.N data which are the results of the calculation of the M.times.N two-dimensional IDCT operator 2. Therefore, M.times.N addition operations are required.